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single-supply, rail-to-rail low power fet-input op amp ad822 rev. i information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1993C2010 analog devices, inc. all rights reserved. features true single-supply operation output swings rail-to-rail input voltage range extends below ground single-supply capability from 5 v to 30 v dual-supply capability from 2.5 v to 15 v high load drive capacitive load drive of 350 pf, g = +1 minimum output current of 15 ma excellent ac performance for low power 800 a maximum quiescent current per amplifier unity-gain bandwidth: 1.8 mhz slew rate of 3 v/s good dc performance 800 v maximum input offset voltage 2 v/c typical offset voltage drift 25 pa maximum input bias current low noise 13 nv/hz @ 10 khz no phase inversion applications battery-powered precision instrumentation photodiode preamps active filters 12-bit to 14-bit data acquisition systems medical instrumentation low power references and regulators connection diagram 1 2 3 4 8 7 6 5 ad822 out1 ?in1 +in1 v? v+ out2 ?in2 +in2 00874-001 figure 1. 8-lead pdip (n suffix); 8-lead msop (rm suffix); and 8-lead soic_n (r suffix) general description the ad822 is a dual precision, low power fet input op amp that can operate from a single supply of 5 v to 30 v or dual supplies of 2.5 v to 15 v. it has true single-supply capability with an input voltage range extending below the negative rail, allowing the ad822 to accommodate input signals below ground in the single-supply mode. output voltage swing extends to within 10 mv of each rail, providing the maximum output dynamic range. frequency (hz) 1 10 10k 1k 100 input voltage noise (nv/ hz) 100 10 00874-002 figure 2. input voltage noise vs. frequency offset voltage of 800 v maximum, offset voltage drift of 2 v/c, input bias currents below 25 pa, and low input voltage noise provide dc precision with source impedances up to a gigaohm. the 1.8 mhz unity-gain bandwidth, C93 db thd at 10 khz, and 3 v/s slew rate are provided with a low supply current of 800 a per amplifier.
ad822 rev. i | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? connection diagram ....................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 4 ? absolute maximum ratings .......................................................... 10 ? thermal resistance .................................................................... 10 ? maximum power dissipation ................................................... 10 ? esd caution ................................................................................ 10 ? typical performance characteristics ........................................... 11 ? applications information .............................................................. 18 ? input characteristics .................................................................. 18 ? output characteristics............................................................... 18 ? single-supply voltage-to-frequency converter .................... 19 ? single-supply programmable gain instrumentation amplifier ..................................................................................... 20 ? low dropout bipolar bridge driver ........................................ 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 22 ? revision history 1/10rev. h to rev. i changes to features section and general description section . 1 changes to endnote 1, table 1 ........................................................ 5 changes to endnote 1, table 2 ........................................................ 7 changes to endnote 1, table 3 ........................................................ 9 deleted table 4; renumbered sequentially ................................ 10 changes to table 5 .......................................................................... 12 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 22 deleted 3 v, single-supply stereo headphone driver section . 22 deleted figure 50; renumbered sequentially ............................ 22 8/08rev. g to rev h. changes to features section and general description section . 1 changed v o to v out throughout ................................................... 4 changes to table 1 ............................................................................ 4 changes to table 2 ............................................................................ 6 changes to table 3 ............................................................................ 8 changes to table 5 .......................................................................... 12 added table 6; renumbered sequentially .................................. 12 changes to figure 13 caption ....................................................... 14 changes to figure 29, figure 31, and figure 35 ......................... 17 changes to figure 36 ...................................................................... 18 changed application notes section to applications information section ....................................................................... 20 changes to figure 46 and figure 47 ............................................. 21 changes to figure 49 ...................................................................... 22 changes to figure 51 ...................................................................... 23 6/06rev. f to rev. g changes to features .......................................................................... 1 changes to table 4 .......................................................................... 10 changes to table 5 .......................................................................... 12 changes to table 6 .......................................................................... 22 10/05rev. e to rev. f updated format .................................................................. universal changes to outline dimensions .................................................. 24 updated ordering guide .............................................................. 24 1/03data sheet changed from rev. d to rev. e edits to specifications ....................................................................... 2 edits to figure 10 ............................................................................ 16 updated outline dimensions ....................................................... 17 10/02data sheet changed from rev. c to rev. d edits to features ................................................................................. 1 edits to ordering guide ................................................................... 6 updated soic package outline ................................................... 17 8/02data sheet changed from rev. b to rev. c all figures updated ................................................................ global edits to features ................................................................................. 1 updated all package outlines ...................................................... 17 7/01data sheet changed from rev. a to rev. b all figures updated ................................................................ global cerdip references removed ....................................... 1, 6, and 18 additions to product description ................................................... 1 8-lead soic and 8-lead msop diagrams added ...................... 1 deletion of ad822s column ........................................................... 2 edits to absolute maximum ratings and ordering guide ......... 6 removed metallization photograph ............................................... 6
ad822 rev. i | page 3 of 24 the ad822 drives up to 350 pf of direct capacitive load as a follower and provides a minimum output current of 15 ma. this allows the amplifier to handle a wide range of load conditions. its combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single-supply user. the ad822 is available in two performance grades. the a grade and b grade are rated over the industrial temperature range of ?40c to +85c. the ad822 is offered in three varieties of 8-lead packages: pdip, msop, and soic_n. 90 100 10 0% . .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... v out 5v 0v (gnd) 1v 20s 1v 1v 0 0874-003 figure 3. gain-of-2 amplifier; v s = 5 v, 0 v, v in = 2.5 v sine centered at 1.25 v, r l = 100
ad822 rev. i | page 4 of 24 specifications v s = 0 v, 5 v @ t a = 25c, v cm = 0 v, v out = 0.2 v, unless otherwise noted. table 1. a grade b grade parameter conditions min typ max min typ max unit dc performance initial offset 0.1 0.8 0.1 0.4 mv maximum offset over temperature 0.5 1.2 0.5 0.9 mv offset drift 2 2 v/c input bias current v cm = 0 v to 4 v 2 25 2 10 pa at t max 0.5 5 0.5 2.5 na input offset current 2 20 2 10 pa at t max 0.5 0.5 na open-loop gain v out = 0.2 v to 4 v r l = 100 k 500 1000 500 1000 v/mv t min to t max 400 400 v/mv r l = 10 k 80 150 80 150 v/mv t min to t max 80 80 v/mv r l = 1 k 15 30 15 30 v/mv t min to t max 10 10 v/mv noise/harmonic performance input voltage noise f = 0.1 hz to 10 hz 2 2 v p-p f = 10 hz 25 25 nv/hz f = 100 hz 21 21 nv/hz f = 1 khz 16 16 nv/hz f = 10 khz 13 13 nv/hz input current noise f = 0.1 hz to 10 hz 18 18 fa p-p f = 1 khz 0.8 0.8 fa/hz harmonic distortion r l = 10 k to 2.5 v f = 10 khz v out = 0.25 v to 4.75 v ?93 ?93 db dynamic performance unity-gain frequency 1.8 1.8 mhz full power response v out p-p = 4.5 v 210 210 khz slew rate 3 3 v/s settling time to 0.1% v out = 0.2 v to 4.5 v 1.4 1.4 s to 0.01% v out = 0.2 v to 4.5 v 1.8 1.8 s matching characteristics initial offset 1.0 0.5 mv maximum offset over temperature 1.6 1.3 mv offset drift 3 3 v/c input bias current 20 10 pa crosstalk @ f = 1 khz r l = 5 k ?130 C130 db crosstalk @ f = 100 khz r l = 5 k ?93 C93 db input characteristics input voltage range 1 , t min to t max ?0.2 +4 ?0.2 +4 v common-mode rejection ratio (cmrr) v cm = 0 v to 2 v 66 80 69 80 db t min to t max v cm = 0 v to 2 v 66 66 db
ad822 rev. i | page 5 of 24 a grade b grade parameter conditions min typ max min typ max unit input impedance differential 10 13 ||0.5 10 13 ||0.5 ||pf common mode 10 13 ||2.8 10 13 ||2.8 ||pf output characteristics output saturation voltage 2 v ol ? v ee i sink = 20 a 5 7 5 7 mv t min to t max 10 10 mv v cc ? v oh i source = 20 a 10 14 10 14 mv t min to t max 20 20 mv v ol ? v ee i sink = 2 ma 40 55 40 55 mv t min to t max 80 80 mv v cc ? v oh i source = 2 ma 80 110 80 110 mv t min to t max 160 160 mv v ol C v ee i sink = 15 ma 300 500 300 500 mv t min to t max 1000 1000 mv v cc ? v oh i source = 15 ma 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 15 15 ma t min to t max 12 12 ma capacitive load drive 350 350 pf power supply quiescent current, t min to t max 1.24 1.6 1.24 1.6 ma power supply rejection v+ = 5 v to 15 v 66 80 70 80 db t min to t max 66 70 db 1 this is a functional specification. amplifier bandwidth decrea ses when the input common-mode voltage is driven in the range (v + ? 1 v) to v+. common-mode error voltage is typically less than 5 mv with the common-m ode voltage set at 1 v be low the positive supply. 2 v ol ? v ee is defined as the difference between the lowest possible output voltage (v ol ) and the negative voltage supply rail (v ee ). v cc ? v oh is defined as the difference between the highest possible output voltage (v oh ) and the positive supply voltage (v cc ).
ad822 rev. i | page 6 of 24 v s = 5 v @ t a = 25c, v cm = 0 v, v out = 0 v, unless otherwise noted. table 2. a grade b grade parameter conditions min typ max min typ max unit dc performance initial offset 0.1 0.8 0.1 0.4 mv maximum offset over temperature 0.5 1.5 0.5 1 mv offset drift 2 2 v/c input bias current v cm = ?5 v to +4 v 2 25 2 10 pa at t max 0.5 5 0.5 2.5 na input offset current 2 20 2 10 pa at t max 0.5 0.5 na open-loop gain v out = ?4 v to +4 v r l = 100 k 400 1000 400 1000 v/mv t min to t max 400 400 v/mv r l = 10 k 80 150 80 150 v/mv t min to t max 80 80 v/mv r l = 1 k 20 30 20 30 v/mv t min to t max 10 10 v/mv noise/harmonic performance input voltage noise f = 0.1 hz to 10 hz 2 2 v p-p f = 10 hz 25 25 nv/hz f = 100 hz 21 21 nv/hz f = 1 khz 16 16 nv/hz f = 10 khz 13 13 nv/hz input current noise f = 0.1 hz to 10 hz 18 18 fa p-p f = 1 khz 0.8 0.8 fa/hz harmonic distortion r l = 10 k f = 10 khz v out = 4.5 v ?93 ?93 db dynamic performance unity-gain frequency 1.9 1.9 mhz full power response v out p-p = 9 v 105 105 khz slew rate 3 3 v/s settling time to 0.1% v out = 0 v to 4.5 v 1.4 1.4 s to 0.01% v out = 0 v to 4.5 v 1.8 1.8 s matching characteristics initial offset 1.0 0.5 mv maximum offset over temperature 3 2 mv offset drift 3 3 v/c input bias current 25 10 pa crosstalk @ f = 1 khz r l = 5 k ?130 ?130 db crosstalk @ f = 100 khz r l = 5 k ?93 ?93 db input characteristics input voltage range 1 , t min to t max ?5.2 +4 ?5.2 +4 v common-mode rejection ratio (cmrr) v cm = ?5 v to +2 v 66 80 69 80 db t min to t max v cm = ?5 v to +2 v 66 66 db input impedance differential 10 13 ||0.5 10 13 ||0.5 ||pf common mode 10 13 ||2.8 10 13 ||2.8 ||pf
ad822 rev. i | page 7 of 24 a grade b grade parameter conditions min typ max min typ max unit output characteristics output saturation voltage 2 v ol ? v ee i sink = 20 a 5 7 5 7 mv t min to t max 10 10 mv v cc ? v oh i source = 20 a 10 14 10 14 mv t min to t max 20 20 mv v ol ? v ee i sink = 2 ma 40 55 40 55 mv t min to t max 80 80 mv v cc ? v oh i source = 2 ma 80 110 80 110 mv t min to t max 160 160 mv v ol ? v ee i sink = 15 ma 300 500 300 500 mv t min to t max 1000 1000 mv v cc ? v oh i source = 15 ma 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 15 15 ma t min to t max 12 12 ma capacitive load drive 350 350 pf power supply quiescent current, t min to t max 1.3 1.6 1.3 1.6 ma power supply rejection v sy = 5 v to 15 v 66 80 70 80 db t min to t max 66 70 db 1 this is a functional specification. amplifier bandwidth decrea ses when the input common-mode voltage is driven in the range (v + ? 1 v) to v+. common-mode error voltage is typically less than 5 mv with the common-m ode voltage set at 1 v be low the positive supply. 2 v ol ? v ee is defined as the difference between the lowest possible output voltage (v ol ) and the negative voltage supply rail (v ee ). v cc ? v oh is defined as the difference between the highest possible output voltage (v oh ) and the positive supply voltage (v cc ).
ad822 rev. i | page 8 of 24 v s = 15 v @ t a = 25c, v cm = 0 v, v out = 0 v, unless otherwise noted. table 3. a grade b grade parameter conditions min typ max min typ max unit dc performance initial offset 0.4 2 0.3 1.5 mv maximum offset over temperature 0.5 3 0.5 2.5 mv offset drift 2 2 v/c input bias current v cm = 0 v 2 25 2 12 pa v cm = ?10 v 40 40 pa at t max v cm = 0 v 0.5 5 0.5 2.5 na input offset current 2 20 2 12 pa at t max 0.5 0.5 na open-loop gain v out = ?10 v to +10 v r l = 100 k 500 2000 500 2000 v/mv t min to t max 500 500 v/mv r l = 10 k 100 500 100 500 v/mv t min to t max 100 100 v/mv r l = 1 k 30 45 30 45 v/mv t min to t max 20 20 v/mv noise/harmonic performance input voltage noise f = 0.1 hz to 10 hz 2 2 v p-p f = 10 hz 25 25 nv/hz f = 100 hz 21 21 nv/hz f = 1 khz 16 16 nv/hz f = 10 khz 13 13 nv/hz input current noise f = 0.1 hz to 10 hz 18 18 fa p-p f = 1 khz 0.8 0.8 fa/hz harmonic distortion r l = 10 k f = 10 khz v out = 10 v ?85 ?85 db dynamic performance unity-gain frequency 1.9 1.9 mhz full power response v out p-p = 20 v 45 45 khz slew rate 3 3 v/s settling time to 0.1% v out = 0 v to 10 v 4.1 4.1 s to 0.01% v out = 0 v to 10 v 4.5 4.5 s matching characteristics initial offset 3 2 mv maximum offset over temperature 4 2.5 mv offset drift 3 3 v/c input bias current 25 12 pa crosstalk @ f = 1 khz r l = 5 k ?130 ?130 db crosstalk @ f = 100 khz r l = 5 k ?93 ?93 db input characteristics input voltage range 1 , t min to t max ?15.2 +14 ?15.2 +14 v common-mode rejection ratio (cmrr) v cm = ?15 v to +12 v 70 80 74 90 db t min to t max v cm = ?15 v to +12 v 70 74 db input impedance differential 10 13 ||0.5 10 13 ||0.5 ||pf common mode 10 13 ||2.8 10 13 ||2.8 ||pf
ad822 rev. i | page 9 of 24 a grade b grade parameter conditions min typ max min typ max unit output characteristics output saturation voltage 2 v ol ? v ee i sink = 20 a 5 7 5 7 mv t min to t max 10 10 mv v cc ? v oh i source = 20 a 10 14 10 14 mv t min to t max 20 20 mv v ol ? v ee i sink = 2 ma 40 55 40 55 mv t min to t max 80 80 mv v cc ? v oh i source = 2 ma 80 110 80 110 mv t min to t max 160 160 mv v ol ? v ee i sink = 15 ma 300 500 300 500 mv t min to t max 1000 1000 mv v cc ? v oh i source = 15 ma 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 20 20 ma t min to t max 15 15 ma capacitive load drive 350 350 pf power supply quiescent current, t min to t max 1.4 1.8 1.4 1.8 ma power supply rejection v sy = 5 v to 15 v 70 80 70 80 db t min to t max 70 70 db 1 this is a functional specification. amplifier bandwidth decrea ses when the input common-mode voltage is driven in the range (v + ? 1 v) to v+. common-mode error voltage is typically less than 5 mv with the common-m ode voltage set at 1 v be low the positive supply. 2 v ol ? v ee is defined as the difference between the lowest possible output voltage (v ol ) and the negative voltage supply rail (v ee ). v cc ? v oh is defined as the difference between the highest possible output voltage (v oh ) and the positive supply voltage (v cc ).
ad822 rev. i | page 10 of 24 absolute maximum ratings table 4. parameter rating supply voltage 18 v internal power dissipation 8-lead pdip (n) observe derating curves 8-lead soic_n (r) observe derating curves 8-lead msop (rm) observe derating curves input voltage 1 ((v+) + 0.2 v) to ((v?) ? 20 v) output short-circuit duration indefinite differential input voltage 30 v storage temperature range (n) C65c to +125c storage temperature range (r, rm) C65c to +150c operating temperature range a grade and b grade C40c to +85c lead temperature (soldering, 60 sec) 260c 1 see the input characteristics section. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. thermal resistance package type ja unit 8-lead pdip (n) 90 c/w 8-lead soic_n (r) 160 c/w 8-lead msop (rm) 190 c/w maximum power dissipation the maximum power that can be safely dissipated by the ad822 is limited by the associated rise in junction temperature. for plastic packages, the maximum safe junction temperature is 145c. if these maximums are exceeded momentarily, proper circuit operation is restored as soon as the die temperature is reduced. leaving the device in the overheated condition for an extended period can result in device burnout. to ensure proper operation, it is important to observe the derating curves shown in figure 27. while the ad822 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. with power supplies 12 v (or less) at an ambient temperature of 25c or less, if the output node is shorted to a supply rail, then the amplifier is not destroyed, even if this condition persists for an extended period. esd caution
ad822 rev. i | page 11 of 24 typical performance characteristics offset voltage (mv) 70 0 ?0.5 ?0.4 number of units ?0.3 ?0.2 ?0.1 0 60 50 40 30 20 10 0.1 0.2 0.3 0.4 0.5 v s = 0v, 5v 00874-004 figure 4. typical distribution of offset voltage (390 units) offset voltage drift (v/c) 16 6 0 ?12 10 ?10 % in bin ?8 ?6 ?4 ?2 14 8 4 2 12 10 86420 v s = 5v v s = 15v 00874-005 figure 5. typical distribution of offset voltage drift (100 units) input bias current (pa) 50 20 0 1 number of units 45 25 15 5 35 30 10 40 0 2345678 910 00874-006 figure 6. typical distribution of input bias current (213 units) common-mode voltage (v) 5 0 ?5 ?5 5 ?4 input bias current (pa) ?3 ?2 ?1 0 1 2 3 4 v s = 5v v s = 0v, +5v and 5v 00874-007 figure 7. input bias current vs. common-mode voltage; v s = 5 v, 0 v, and v s = 5 v common-mode voltage (v) 1k 100 0.1 ?16 16 ?12 input bias current (pa) ?8 ?4 0 4 8 12 10 1 00874-008 figure 8. input bias current vs. common-mode voltage; v s = 15 v temperature (c) 100k 0.1 20 140 40 input bias current (pa) 60 80 100 120 10k 1k 100 10 1 00874-009 figure 9. input bias current vs. temperature; v s = 5 v, v cm = 0 v
ad822 rev. i | page 12 of 24 load resistance ( ? ) 10m 1m 10k 100 100k open-loop gain (v/v) 100k 1k 10k v s = 0v, +5v v s = 15v v s = 0v, +3v 00874-010 figure 10. open-loop gain vs. load resistance temperature (c) 10m 1m 10k ?60 140 ?40 open-loop gain (v/v) ?20 0 20 40 60 80 100 120 100k r l = 100k ? r l = 10k ? r l = 600 ? v s = 15v v s = 0v, +5v v s = 15v v s = 0v, +5v v s = 15v v s = 0v, +5v 00874-011 figure 11. open-loop gain vs. temperature output voltage (v) 300 ?300 ?16 16 ?12 input error voltage (v) ?8 ?4 0 4 8 12 200 100 0 ?100 ?200 r l = 100k ? r l = 10k ? r l = 600 ? 00874-012 figure 12. input error voltage vs. output voltage for resistive loads output voltage from supply rails (mv) 40 20 ?40 60 input error voltage (v) 120 180 240 0 ?20 pos rail neg rail neg rail neg rail pos rail r l = 20k ? r l = 2k ? r l = 100k ? pos rail 0 300 00874-013 figure 13. input error voltage with outp ut voltage within 300 mv of either supply rail for various resistive loads; v s = 5 v frequency (hz) 1k 100 1 10 1k 10 11 0 k 100 input voltage noise (nv/ hz) 00874-014 figure 14. input voltage noise vs. frequency frequency (hz) ? 40 ?50 ?110 100 100k 1k thd (db) 10k ?70 ?80 ?90 ?100 ?60 r l = 10k ? a cl = ?1 v s = 0v, +3v; v out = 2.5v p-p v s = 15v; v out = 20v p-p v s = 5v; v out = 9v p-p v s = 0v, +5v; v out = 4.5v p-p 00874-015 figure 15. total harmonic distortion (thd) vs. frequency
ad822 rev. i | page 13 of 24 frequency (hz) 100 ?20 80 60 40 20 0 10 10m 100 open-loop gain (db) 1k 10k 100k 1m 100 ?20 80 60 40 20 0 phase margin (degrees) phase gain c l = 100pf r l = 2k ? 00874-016 figure 16. open-loop gain and phase margin vs. frequency frequency (hz) 1k 100 100 10m 1k output impedance ( ? ) 10k 100k 1m 10 1 0.1 0.01 a cl = +1 v s = 15v 00874-017 figure 17. output im pedance vs. frequency settling time (s) 16 12 ?16 05 1 output swing from 0 to volts 234 0 ?4 ?8 ?12 8 4 error 1% 0.1% 1% 0.01% 0.01% 0 0874-018 figure 18. output swing and error vs. settling time 90 80 0 40 30 20 10 60 50 70 common-mode rejection (db) frequency (hz) 10m 100 1k 10k 100k 1m 10 v s = 15v v s = 0v, +5v v s = 0v, +3v 00874-019 figure 19. common-mode rejection vs. frequency +125c ?55c +25c positive rail negative rail common-mode voltage from supply rails (v) 5 4 0 ?1 3 common-mode error voltage (mv) 3 2 1 ?55c +125c 2 1 0 00874-020 figure 20. absolute common-mode error vs. common-mode voltage from supply rails (v s ? v cm ) load current (ma) 1000 100 0 0.001 100 0.01 output s a tur a tion vol t age (mv) 0.1 1 10 10 v s ? v oh v ol ? v s 00874-021 figure 21. output saturation voltage vs. load current
ad822 rev. i | page 14 of 24 temperature (c) 1000 100 1 ?60 140 ?40 output s a tur a tion voltage (mv) ?20 0 20 40 60 80 100 120 10 i source = 10ma i sink = 10ma i source = 1ma i sink = 1ma i source = 10a i sink = 10a 00874-022 figure 22. output saturation voltage vs. temperature temperature (c) 80 40 0 ?60 140 ?40 ?20 0 20 40 60 80 100 120 sho r t-circuit current limit (ma) 70 60 20 10 50 30 + ? ? + + ?out v s = 15v v s = 15v v s = 0v, +5v v s = 0v, +3v v s = 0v, +5v v s = 0v, +3v 00874-023 figure 23. short-circuit cu rrent limit vs. temperature total supply voltage (v) 1600 0 4 quiescent current (a) 1400 800 600 400 200 1200 1000 t = +125c t = +25c t = ?55c 36 32 2824201612 08 00874-024 figure 24. quiescent current vs. supply voltage vs. temperature frequency (hz) 100 0 10 10m 100 power supply rejection (db) 1k 10k 100k 1m 90 60 30 20 10 80 70 50 40 +psrr ?psrr 00874-025 figure 25. power supply rejection vs. frequency frequency (hz) 30 25 0 10k 10m 100k output voltage (v) 1m 20 15 10 5 v s = 15v v s = 0v, +5v v s = 0v, +3v r l = 2k ? 00874-026 figure 26. large signal frequency response ambient temperature (c) 2.4 1.2 0.4 ?60 ?40 ?20 0 20 40 60 80 2.2 1.4 1.0 0.6 1.8 1.6 0.8 2.0 0.2 0 8-lead pdip 8-lead soic 8-lead msop total power dissip a tion (w) 00874-027 figure 27. maximum power dissipation vs. temperature for packages
ad822 rev. i | page 15 of 24 frequency (hz) ? 70 ?140 300 1m 1k 3k 10k 30k 100k 300k ?80 ?100 ?110 ?120 ?130 ?90 crosstalk (db) 00874-028 figure 28. crosstalk vs. frequency v in r l v out 100pf 8 v + 0.01f 4 0.01f 1/2 ad822 + ? 00874-029 figure 29. unity-gain follower 0% 100 90 10 5v 10s 00874-030 figure 30. 20 v p-p, 25 khz sine wave input; unity-gain follower; v s = 15 v, r l = 600 v+ 20v p- p 2 3 8 5 6 20k ? 2.2k ? 5k? 5k? v out crosstalk = 20 log v out 10v in 0.1f 1f 0.1f 1f v? v in + ? 1/2 ad822 1 + ? 1/2 ad822 7 00874-031 figure 31. crosstalk test circuit 0% 100 90 10 5v 5s 00874-032 figure 32. large signal response unity-gain follower; v s = 15 v, r l = 10 k 10 0% 100 90 10mv 500ns 00874-033 figure 33. small signal response unity-gain follower; v s = 15 v, r l = 10 k gnd 10 0% 100 90 1v 2s 00874-034 figure 34. v s = 5 v, 0 v; unity-gain follower response to 0 v to 4 v step 4 v in r l v out 100pf 8 v + 0.01f 1/2 ad822 + ? 0 0874-035 figure 35. unity-gain follower
ad822 rev. i | page 16 of 24 20k? 10k ? 4 100pf v in r l v out 8 v+ 0.01f + ? 1/2 ad822 00874-036 figure 36. gain-of-two inverter gnd 10 0% 100 90 2s 1v 00874-037 figure 37. v s = 5 v, 0 v; unity-gain follower response to 0 v to 5 v step gnd 10 0% 100 90 10mv 2s 00874-038 figure 38. v s = 5 v, 0 v; unity-gain follower response to 40 mv step, centered 40 mv above ground, r l = 10 k gnd 10 0% 100 90 10mv 2s 0 0874-039 figure 39. v s = 5 v, 0 v; gain-of-2 inverter response to 20 mv step, centered 20 mv below ground, r l = 10 k gnd 10 0% 100 90 1v 2s 00874-040 figure 40. v s = 5 v, 0 v; gain-of-2 inverter response to 2.5 v step, centered ?1.25 v below ground, r l = 10 k g nd 10 0% 100 90 500mv 10s 00874-041 figure 41. v s = 3 v, 0 v; gain-of-2 inverter, v in = 1.25 v, 25 khz, sine wave centered at ?0.75 v, r l = 600
ad822 rev. i | page 17 of 24 (a) gnd v in v out 5v r p 90 100 10 0% .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... 1v 10s 1v (b) gnd +v s 90 100 10 0% .... .... .... .... ... ... .... .... .... .... .... .... .... .... .... .... .... .... .... .... 1v 10s 1v 1v 00874-042 figure 42. (a) response with r p = 0; v in from 0 v to +v s (b) v in = 0 v to +v s + 200 mv v out = 0 v to +v s r p = 49.9 k
ad822 rev. i | page 18 of 24 applications information input characteristics in the ad822, n-channel jfets are used to provide a low offset, low noise, high impedance input stage. minimum input common- mode voltage extends from 0.2 v below ?v s to 1 v less than +v s . driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in figure 34 and figure 37) and increased common-mode voltage error as illustrated in figure 20. the ad822 does not exhibit phase reversal for input voltages up to and including +v s . figure 42 shows the response of an ad822 voltage follower to a 0 v to 5 v (+v s ) square wave input. the input and output are superimposed. the output tracks the input up to +v s without phase reversal. the reduced bandwidth above a 4 v input causes the rounding of the output waveform. for input voltages greater than +v s , a resistor in series with the ad822 noninverting input prevents phase reversal, at the expense of greater input voltage noise. this is illustrated in figure 42. because the input stage uses n-channel jfets, input current during normal operation is negative; the current flows out from the input terminals. if the input voltage is driven more positive than +v s ? 0.4 v, then the input current reverses direction as internal device junctions become forward biased. this is illu- strated in figure 7. a current limiting resistor should be used in series with the input of the ad822 if there is a possibility of the input voltage exceed- ing the positive supply by more than 300 mv, or if an input voltage is applied to the ad822 when +v s or ?v s = 0 v. the amplifier is damaged if left in that condition for more than 10 seconds. a 1 k resistor allows the amplifier to withstand up to 10 v of conti- nuous overvoltage and increases the input voltage noise by a negligible amount. input voltages less than ?v s are a completely different story. the amplifier can safely withstand input voltages 20 v below the negative supply voltage if the total voltage from the positive supply to the input terminal is less than 36 v. in addition, the input stage typically maintains picoampere (pa) level input currents across that input voltage range. the ad822 is designed for 13 nv/hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to figure 14). this noise performance, along with the ad822 low input current and current noise, means that the ad822 contributes negligible noise for applications with source resistances greater than 10 k and signal bandwidths greater than 1 khz. this is illustrated in figure 43. 100k 0.1 10k 1k 100 10 1 whenever johnson noise is greater than amplifier noise, amplifier noise can be considered negligible for application. 1khz amplifier-generated noise 10hz 10k 100k 1m 10m 100m 1g 10g source impedance ( ? ) input vol t age noise (v) resistor johnson noise 00874-043 figure 43. total noise vs. source impedance output characteristics the ad822 unique bipolar rail-to-rail output stage swings within 5 mv of the negative supply and 10 mv of the positive supply with no external resistive load. the approximate output saturation resistance of the ad822 is 40 sourcing and 20 sinking, which can be used to estimate output saturation voltage when driving heavier current loads. for instance, when sourcing 5 ma, the saturation voltage to the positive supply rail is 200 mv; when sinking 5 ma, the saturation voltage to the negative rail is 100 mv. the open-loop gain characteristic of the amplifier changes as a function of resistive load, as shown in figure 10 to figure 13. for load resistances over 20 k, the ad822 input error voltage is virtually unchanged until the output voltage is driven to 180 mv of either supply. if the ad822 output is overdriven so that either of the output devices are saturated, the amplifier recovers within 2 s of its input returning to the linear operating region of the amplifier. direct capacitive loads interact with the effective output imped- ance of the amplifier to form an additional pole in the amplifier feedback loop, which can cause excessive peaking on the pulse response or loss of stability. the worst case occurs when the amplifier is used as a unity-gain follower. figure 44 shows the ad822 pulse response as a unity-gain follower driving 350 pf. this amount of overshoot indicates approximately 20 of phase marginthe system is stable, but nearing the edge. configurations with less loop gain, and as a result less loop bandwidth, are much less sensitive to capacitance load effects.
ad822 rev. i | page 19 of 24 90 .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... .... 100 0% 10 20mv 2s 00874-044 figure 44. small signal response of ad822 as unity-gain follower driving 350 pf figure 45 is a plot of noise gain vs. capacitive load that results in a 20 phase margin for the ad822. noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. 1 2 3 4 5 300 1k 3k 10k 30k capacitive load for 20 phase margin (pf) noise gain 1+ r f r 1 r1 r f c l 00874-045 figure 45. noise gain vs. capacitive load tolerance figure 46 shows a method for extending capacitance load drive capability for a unity-gain follower. with these component values, the circuit drives 5000 pf with a 10% overshoot. 20pf 100 ? 20k ? 8 4 v in v + 0.01f v out 0.01f c l 1/2 ad822 + ? v? 00874-046 figure 46. extending unity-gain follower capacitive load capability beyond 350 pf single-supply voltage-to-frequency converter the circuit shown in figure 47 uses the ad822 to drive a low power timer that produces a stable pulse of width t 1 . the positive going output pulse is integrated by r1 and c1 and used as one input to the ad822 that is connected as a differential integrator. the other input (nonloading) is the unknown voltage, v in . the ad822 output drives the timer trigger input, closing the overall feedback loop. 2 3 4 6 5 u3a u3b c3 0.1 f 123 4 out2 out1 u1 c1 u2 cmos 555 thr tr dis gnd out cv 1 2 3 4 5 6 7 8 rv+ c4 0.01f r3 116k ? 0.01f, 2% cmos 74hco4 r scale 10k ? u4 ref02 v ref = 5v 10v c5 0.1f r2 499k ? 1% r1 499k ? 1% v in c2 0.01f 2% 0v to 2.5v full scale 1/2 ad822b + ? notes 1. f out = v in / (v ref t 1 ), t 1 = 1.1 r3 c6. 2. r3 = 1% metal film <50ppm/c tc. 3. r scale = 10% 20t film <100ppm/c tc. 4. t 1 = 33f for f out = 20khz @ v in = 2.0v. = 25khz f s as shown. 00874-047 figure 47. single-supply volt age-to-frequency converter typical ad822 bias currents of 2 pa allow m range source impedances with negligible dc errors. linearity errors on the order of 0.01% full scale can be achieved with this circuit. this performance is obtained with a 5 v single supply that delivers less than 1 ma to the entire circuit.
ad822 rev. i | page 20 of 24 single-supply programmable gain instrumentation amplifier the ad822 can be configured as a single-supply instrumenta- tion amplifier that is able to operate from single supplies down to 3 v or dual supplies up to 15 v. using only one ad822 rather than three separate op amps, this circuit is cost and power efficient. the 2 pa bias currents of the ad822 fet inputs minimize offset errors caused by high unbalanced source impedances. an array of precision thin film resistors sets the in-amp gain to be either 10 or 100. these resistors are laser trimmed to ratio match to 0.01% and have a maximum differential tc of 5 ppm/c. table 6. in-amp performance parameters v s = 3 v, 0 v v s = 5 v cmrr 74 db 80 db common-mode voltage range ?0.2 v to +2 v ?5.2 v to +4 v 3 db bw g = 10 180 khz 180 khz g = 100 18 khz 18 khz t settling 2 v step 2 s 5 v step 5 s noise @ f = 1 khz g = 10 270 nv/hz 270 nv/hz g = 100 2.2 v/hz 2.2 v/hz i supply (total) 1.10 ma 1.15 ma 90 100 10 0% .... .... .... .... ... ... .... .... .... .... .... .... .... .... .... .... .... .... .... .... 1v 5s 00874-048 figure 48. pulse response of in-a mp to a 500 mv p-p input signal; v s = 5 v, 0 v; gain = 0 g = 100 g = 100 g = 10 g = 10 1 2 3 4 5 6 7 + ? + ? 00874-049 ohmtek part # 1043 r5 9k ? r4 1k ? r3 1k ? r2 9k ? r1 90k ? r6 90k ? v ref v + 0.1f 1/2 ad822 1/2 ad822 v out + ? + ? v in1 v in2 r p 1k ? r p 1k ? (g = 10) v out = (v in1 ? v in2 )+ v ref 1+ r6 r4 + r5 () (g = 100) v out = (v in1 ? v in2 )+ v ref r5 + r6 r4 1+ () figure 49. a single-supply progra mmable instrumentation amplifier low dropout bipolar bridge driver the ad822 can be used for driving a 350 wheatstone bridge. figure 50 shows one-half of the ad822 being used to buffer the ad589 , a 1.235 v low power reference. the output of 4.5 v can be used to drive an analog-to-digital converter (adc) front end. the other half of the ad822 is configured as a unity-gain inverter and generates the other bridge input of ?4.5 v. resistor r1 and resistor r2 provide a constant current for bridge excitation. the ad620 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. the gain of the ad620 is programmed using an external resistor r g and determined by 1 k9.49 ? ? ? g r g +1.235v 49.9k ? r1 20 ? 25.4k ? 1% 10k ? 1% 350 ? 350 ? 350 ? 350 ? r g ad589 10k ? 1% 10k ? 1% r2 20 ? ?4.5v gnd +5v ?5v 1/2 ad822 + ? + ? 1/2 ad822 8 3 2 1 v + +v s ?v s v ref v+ v? v? + ? ad620 + ? 2 3 4 5 6 7 0.1 f 0.1 f 1 f 1 f ++ ++ 6 5 7 4 to a/d converter reference input 00874-051 figure 50. low dropout bipolar bridge driver
ad822 rev. i | page 21 of 24 outline dimensions compliant to jedec standards ms-001 controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. 070606-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) seating plane 0.015 (0.38) min 0.210 (5.33) max 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) bsc 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) gauge plane 0.005 (0.13) min figure 51. 8-lead plastic dual in-line package [pdip] narrow body (n-8) dimensions shown in inches and (millimeters) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 52. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 100709-b 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 53. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters
ad822 rev. i | page 22 of 24 ordering guide model 1 temperature range package description package option branding ad822an ?40c to +85c 8-lead pdip n-8 ad822anz ?40c to +85c 8-lead pdip n-8 ad822ar ?40c to +85c 8-lead soic_n r-8 ad822ar-reel ?40c to +85c 8-lead soic_n r-8 ad822ar-reel7 ?40c to +85c 8-lead soic_n r-8 ad822arz ?40c to +85c 8-lead soic_n r-8 ad822arz-reel ?40c to +85c 8-lead soic_n r-8 ad822arz-reel7 ?40c to +85c 8-lead soic_n r-8 ad822armz ?40c to +85c 8-lead msop rm-8 #b4a ad822armz-reel ?40c to +85c 8-lead msop rm-8 #b4a ad822br ?40c to +85c 8-lead soic_n r-8 ad822br-reel ?40c to +85c 8-lead soic_n r-8 ad822br-reel7 ?40c to +85c 8-lead soic_n r-8 AD822BRZ ?40c to +85c 8-lead soic_n r-8 AD822BRZ-reel ?40c to +85c 8-lead soic_n r-8 AD822BRZ-reel7 ?40c to +85c 8-lead soic_n r-8 1 z = rohs compliant part, # denotes rohs-compliant product may be top or bottom marked. spice model is available at www.analog.com .
ad822 rev. i | page 23 of 24 notes
ad822 rev. i | page 24 of 24 notes ?1993C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00874-0-1/10(i)

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